The preferred embodiment of the present invention is used for dynamic pole-zero reconfiguration of phase lock loop ("PLL") used to recover data in a hard disc storage system. For that reason, the background of this invention will be described with respect to controlling PLL bandwidth and damping ratio characteristics. However, the present invention may be used to dynamically reconfigure other electronic circuits whose transfer function is affected by repositioning at least one pole and/or a zero.
As shown by FIG. 1, a conventional magnetic disc storage system 2 includes one or more magnetic storage platters or discs 4, 6 that are rotated with velocity .omega. by a spindle motor 8. Discs 4, 6 have respective upper and lower surfaces 4U, 4L, 6U, 6L upon which data may be magnetically written or read. More specifically, projecting arms of an actuator carriage 10 carry read/write heads (hereafter "heads") 12U, 12L, 14U, 14L that respectively read and/or write data from disc surfaces 4U, 4L, 6U, 6L. Actuator carriage 10 moves all heads radially under command of a positioning servo controller mechanism 16. Of course, assembly 2 is contained in a suitably sealed protective housing (not shown).
The various surfaces of discs 4, 6 are commonly formatted into concentric tracks, T1, T2, T3, etc., portions of which are defined as pie-shaped wedges or sectors, e.g., S1, S2, etc. As such, the various disc storage locations may be defined by disc number (e.g., disc 4), disc surface (e.g., 4U), track (or cylinder) number (e.g., T3) and sector number (e.g., sector S1).
System 2 is coupled to a host computer (not shown). In response to commands issued by users of the host computer, or by a program under execution by the host computer, an appropriate disc drive interface command is issued. For example, such command may require the servo controller 16 to seek data or a storage location on one of the surfaces of a disc, e.g., disc 4, surface 4U, track T3, sector S2.
In response to this command, servo controller 16 actuates carriage 10 in a controlled fashion to move all heads 12U, 12L, 14U, 14L in unison over the disc surfaces until the heads are positioned over the desired target track, T3 in the example at hand. Since all heads on the carriage move together, system 2 includes control circuitry to select the proper read/write head to perform the desired data transfer function, head 12U in the present example. It is expected that system 2 should access data from the target within ten milliseconds or so.
In some storage systems, a dedicated disc surface, surface 4U for example, is provided upon which positional information is permanently pre-recorded for use by servo mechanism 16. More modern storage systems record servo data interspersed with user data, thus avoiding dedication of an entire disc surface to servo signals.
In each system, demodulation of the servo information permits derivation of read/write head position.
As the read/write heads move over the various disc surfaces, a stream of detected or recovered signals is input to a data recovery system 18. Data recovery system 18 includes a clock recovery circuit 20 that typically includes a PLL 24, associated PLL compensation circuitry 26, and toggle circuitry 28. Those skilled in the art will recognize that the data stream provided by the read/write heads is modulated both in frequency and in phase, as a function of the radial position of the read/write heads relative to the disc. Because neither frequency nor phase is known absolutely, it can be difficult to discern at a given moment in time whether the present data stream is useful data, servo data, or garbage.
In conventional clock recovery circuits 20, it is the function of PLL 24 to lock onto the long term average of the recovered data and to generate a series of reference windows in time. The output of PLL 24 as well as the recovered data stream are input to toggle circuitry 28, which typically comprises a series-coupled pair of D-type flipflops. The flipflops toggle with each magnetic transition of the recovered data and the second flipflop is reset with one of the complementary outputs of the PLL 24. As a result, it is possible for the data recovery circuit 18 to output recovered data (to the exclusion of servo data or garbage) to other circuitry, not shown in FIG. 1, for further signal processing by a host computer.
FIG. 2 depicts a typical PLL such as may be used for PLL 24 in FIG. 1. PLL 24 includes a phase detector 30, a loop lowpass filter 32 whose pole-zero characteristics help determine compensation for PLL 24, a voltage controlled oscillator ("VCO") that typically receives current and voltage inputs, and a frequency divider 36. Typically each element in FIG. 2 receives and outputs two signals that are complementary. As is known in the art, phase detector 30 compares input signals f1 to output signals f2/N and outputs a phase error signal that is filtered by loop filter 32 to provide control signals that cause VCO 34 to increase or decrease frequency to minimize the phase error signal. By way of example, if PLL 24 is used to implement a frequency synthesizer, wherein N=10, it is understood that f2 will be ten times the frequency of f1.
Those skilled in the art will recognize that lowpass filter 32 (or other compensation circuit) has an output signal/input signal transfer function that can be represented by the locations of poles and zeroes in the S-plane, where S is the Laplacian transform, -j.omega.. For example, a transfer function expressed as T(S)=(S-S1)/(S-S2) is said to have a zero at S=S1, and a pole at S=S2.
The location of the poles and zeroes of the compensation circuit (e.g., filter 32) help determine the bandwidth and damping factor (.zeta.) of the PLL 24. Ideally, PLL 24 should simultaneously present a large bandwidth during data recovery and a fast recovery or lock time. For example, PLL 24 may have gain and phase characteristics similar to what is shown in either the left-hand or right-hand portion of FIG. 6B.
As noted, PLL performance is affected by the compensation characteristics. FIGS. 3A and 3B depict respectively a simple and a more complex form of type 2 compensation that can be used to compensate a PLL. With reference to FIG. 1, the configuration of 3A or 3B could be used as compensation 26, and with reference to FIG. 2, these configurations could be used as the lowpass loop filter 32.
For the simple compensation configuration of FIG. 3A, the transfer function is given by: ##EQU1## where S is the Laplacian operator, S=-j.omega..
While the circuit of FIG. 3A is simple and straightforward, it only provides single pole rolloff for sampling frequency feedthrough and noise. By contrast, the improved type 2 compensation shown in FIG. 3B increases the rejection of sampling frequency feedthrough and noise, but at the expense of additional phase shift.
For the improved 2 compensation configuration of FIG. 3B, the transfer function is given by: ##EQU2## where g (S)=S.sup.2 +S{[1/RC.sub.1 ]+[1/R.sub.2 C.sub.2 ]+[1//R.sub.2 C.sub.1 ]+[1/R.sub.2 C]}+{[C+C.sub.2 ]/RR.sub.2 CC.sub.1 C.sub.2 }
The above equation for T may be broken down into four component parts as follows:
(a) a gain term, given by: ##EQU3##
(b) a zero located at S=1/R[C+C.sub.1 ];
(c) a pole located at the origin, (resulting from 1/S); and
(d) a two pole lowpass filter, represented by: [S.sup.2 +S{[1/RC.sub.1 ]+[1/R.sub.2 C.sub.2 ]+[1/R.sub.2 C.sub.1 ]+[1/R.sub.2 C]}+{[C+C.sub.2 ]/RR.sub.2 C.sub.1 C.sub.2 }].sup.-1, which has the form [S.sup.2 +2.zeta..omega..sub.n S+.omega..sub.n.sup.2 ].sup.-1.
Unfortunately, as noted, in modern hard disc systems, the recovered data varies in frequency with the radial position of the read/write head. What may be a relatively optimum PLL compensation for data at certain tracks on the hard discs may in fact be detrimental compensation when reading data located at other tracks. Thus, in practice, the PLL gain and damping factors generally are specified for a nominal recovered data frequency and for a compromise gain and damping factor. Typically the resistors R and capacitors C controlling the compensation are discrete components, mounted on a printed circuit board and coupled to an integrated circuit associated with PLL 24.
It is known in the art to vary the PLL compensation by varying open loop gain, but so doing can undesirably alter the PLL damping ratio .zeta.. One could mitigate the undesired effect upon damping ratio by widely separating the frequency location of the PLL pole and zero. However as the pole-zero span is increased, the high frequency pole contributes less effectively to the desired filtering. In addition, widely separating the pole and zero can result in undesired PLL oscillations if the gain is maintained at too high a magnitude.
In summary, there is a need for a mechanism that permits reconfiguring the pole-zero compensation for a PLL on-the-fly, such that compensation may be dynamically altered to accommodate varying input data frequencies.
Preferably such mechanism should be fabricated on the same integrated circuit chip containing the PLL.
The present invention discloses such a system, and a generalized method for implementing its use.